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HARDWARE · QUANTUM CONTROL AND DECODING

Alice & Bob’s GPU Decoding Test Uses Synthetic Errors

The NVQLink proof of concept connects control electronics to GPU decoding. It does not yet perform real-time error correction.

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An open QICK electronics enclosure with densely connected circuit boards under red and blue lighting.
A QICK quantum readout and control box at Fermilab. Archival context for quantum-control electronics; this is not the OPX1000, GPU or apparatus used in Alice & Bob’s test.Ryan Postel / Fermilab · National Quantum Initiative gallery reuse permission; attribution requiredFull image credit

Alice & Bob reported an October 13 test of GPU decoding for its LDPC-cat codes using NVIDIA NVQLink and Quantum Machines’ OPX1000 controller. The input was synthetic data. The company explicitly says the implementation is not real-time decoding.[1]

The code family targets a particular kind of quantum hardware. Cat suppress bit-flip errors, leaving phase errors as the principal correction task. The January 2025 architecture paper combines that bias with low-density parity-check codes to reduce qubit overhead. Those modeled resource savings do not establish the speed of an implemented decoder.[2]

The interface is the new engineering focus. In Quantum Machines’ documented workflow, a controller streams measurement records to a classical accelerator, which calculates corrections and returns information for subsequent control. The vendor reports communication below four microseconds for an OPX1000–GraceHopper pairing. This is a link specification, not a measured Alice & Bob decoding response time.[3]

Alice & Bob reports greater efficiency when several error records are decoded together. Its announcement supplies no end-to-end latency or decoder-accuracy benchmark table. The stated next step is pipeline optimization. Synthetic inputs and batch processing leave a live feedback demonstration outstanding.[1]

A useful comparison is a separate June 2026 Riverlane–Rigetti experiment. Its FPGA decoder and superconducting processor completed a nine-round feedback test with a measured 9.6-microsecond response. That is a different code, processor and accelerator; it illustrates an end-to-end measurement, not an interchangeable performance target.[4]

QubitWire’s analysis: the practical advance to look for is a decoder becoming a working part of a control system. Three checks should remain separate: whether records arrive correctly, whether the inferred correction is reliable, and whether the returned decision arrives when the quantum program needs it. Passing one does not establish the other two.[3][4]

The next informative test would publish the exact code and workload, then use measured quantum error records to report accuracy and complete response-time distributions. Transfer, queueing, computation and return traffic should all be counted. A same-workload comparison against an existing decoder would show what the GPU integration actually buys.[3][4]

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Evidence & context

4 linked sources

Company-reported synthetic-input integration test. Historical papers and controller documentation provide context, not independent replication.

How to read the evidence and dates

An announcement records what an organization stated. An experiment reports an observation. A simulation or resource estimate depends on its assumptions. QubitWire’s analysis connects these sources; the labels are not quality scores.

Published is the article’s first QubitWire publication. Updated marks a substantive content change. Sources checked records a review of the underlying evidence. An older paper can support a new explanation, and another press release about the same work is not independent replication.

QubitWire take

An integrated decoder needs three checks: correct data transfer, reliable error inference and timely feedback. Test each on the same workload.

Sources

  1. Alice & Bob: October 13 decoding announcement

    Company-reported integration proof of concept; retrieved as indexed official text. Direct page access returned a challenge.

  2. Ruiz et al.: LDPC-cat architecture, January 2025

    Peer-reviewed theoretical and numerical background; not validation of the October implementation.

  3. Quantum Machines: Open Acceleration Stack documentation

    Vendor documentation; communication figures are not the candidate’s complete decoder timing.

  4. Caune et al.: real-time superconducting QEC, June 2026

    Separate hardware experiment. Different code and implementation; historical benchmark context.

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    An October 2 preprint reports modular neural decoding of IBM memory and lattice-surgery experiments. Reusing the architecture reduces redesign, but live processing speed remains unmeasured.

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    Riverlane and Rigetti Demonstrate Fast Live Error Decoding

    An eight-qubit experiment reports mean decoding below one microsecond per round, with complete feedback measured separately.

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