Alice & Bob tests cat-qubit building blocks, with threshold still ahead

What the hardware shows

Alice & Bob says it has assembled and operated three cat-qubit demonstrators for Phase 1 of France’s PROQCIMA programme: two six-qubit chips and one twelve-qubit chip. The October 20 announcement describes the building blocks of its error-correction architecture on real hardware.^[1]

The reported work includes noise-biased CNOT gates, auxiliary-qubit measurement and reset, repeated cycles of a distance-three repetition code and a non-Clifford operation. The company also measured logical error across the register. Its key qualification is explicit: that logical error rate is not yet below threshold.^[1]

Why the threshold matters

That boundary belongs beside the result. Demonstrating the required ingredients is a different engineering task from showing that the assembled system suppresses errors sufficiently to support a useful logical computation. The announcement should be read as progress toward that integration test.

Alice & Bob says a digital twin built from measured device performance identifies improvements needed to reach below-threshold operation, beginning with more consistent coherence across the chip. Those simulations are a guide to the next experiment, rather than a measurement that the target has been reached.^[1]

The next question

For readers comparing architectures, the next useful report would put the whole operating sequence on one clock: error checks, logical operations, classical decisions, recalibration and final output. A clear denominator would show which failure rate applies to which task.

QubitWire’s reading is that the integration work matters precisely because the remaining boundary is visible. A roadmap for universal fault tolerance and a measured result from a demonstrator serve different purposes. Keeping both in view makes the next milestone easier to judge.