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Double-Resonator Coupler Design Simulates a 20-Nanosecond CZ Gate

A proposed superconducting circuit uses two resonator paths to suppress idle coupling, but its speed and error figures remain simulation results.

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Conceptual diagram of two superconducting qubits connected through two resonator paths and a tunable junction, with idle and activated interaction states.
Conceptual view of the proposed double-resonator coupler: two abstract resonator paths link physical qubits through a tunable junction. This original diagram is not a fabricated device, measured layout or reproduction of the preprint's figures.Original QubitWire conceptual diagram based on factual architecture descriptions in Seunghyeon Jin et al., arXiv:2609.05222 (2026). Illustration: QubitWire · Original QubitWire workFull image credit

A Seoul National University and Samsung-affiliated team has proposed a double-resonator coupler for superconducting transmon qubits. Two resonator modes, joined by one , create competing virtual exchange paths whose interference can tune the interaction between neighboring physical qubits. That mechanism targets a persistent hardware trade-off: neighboring qubits should interact strongly during a gate but remain effectively isolated while idle. A broader low-coupling operating region could ease frequency allocation, although the paper's parameter sweep shows that greater flexibility weakens the available activated interaction.

For one modeled parameter set, numerical diagonalization finds two flux biases with zero residual ZZ interaction outside the straddling regime while nearby transverse coupling stays below 1 MHz. The activated ZZ interaction reaches 69.2 MHz, and an optimized simulated 20-nanosecond pulse has coherent infidelity near 1e-5.

Those numbers do not come from a fabricated device. With an assumed 50-microsecond T1 for qubits and coupler modes, the authors estimate relaxation infidelity of 3e-4; an assumed flux-noise model adds 1.6e-5. Shortening the simulated pulse to 16 nanoseconds pushes coherent infidelity toward 1e-3, underscoring the speed-error trade-off.

The decisive next step is fabrication and calibration, followed by leakage, crosstalk and randomized-benchmarking measurements across realistic device variation. Larger-processor tests would also need to show that the extra resonators and flux controls improve usable connectivity without introducing new frequency-crowding or control overhead.

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Evidence & context

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Unreviewed September 4, 2026 preprint from Seoul National University and Samsung-affiliated authors. Every gate speed and error figure is calculated or simulated for a proposed circuit under stated coherence and noise assumptions; no coupler was fabricated or benchmarked.

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An announcement records what an organization stated. An experiment reports an observation. A simulation or resource estimate depends on its assumptions. QubitWire’s analysis connects these sources; the labels are not quality scores.

Published is the article’s first QubitWire publication. Updated marks a substantive content change. Sources checked records a review of the underlying evidence. An older paper can support a new explanation, and another press release about the same work is not independent replication.

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