QC Design
Plaquette lets hardware teams compare error-correcting codes and architectures under device-specific noise, including leakage and coherent errors that simpler noise models can miss.
Germany · Research reviewed 7 Sept 2026Latest record: research brief added · axis ratings unchanged.
Review history 2 records
Record dates show when an assessment or clarification was saved. Review dates show the evidence check. Earlier records were recovered from QubitWire’s source history; no earlier score movement is inferred.
Research brief added · axis ratings unchanged
Assessment reviewed 6 Sept 2026 · Research reviewed 7 Sept 2026What changed
- Research brief
- PreviouslyNone recorded
- NowInitial technology, access and evidence brief
Sources in this record (4)
- Plaquette — QC Design ↗
- Yaqumo and QC Design Announce Collaboration to Accelerate Fault-Tolerant Neutral-Atom Quantum Computing ↗
- Plaquette: A hardware-aware design platform for fault-tolerant quantum computers ↗
- C12 Partners with QC Design and Adopts Plaquette to accelerate towards Fault-Tolerant Quantum Computing with Carbon Nanotubes ↗
Initial assessment recorded
Assessment reviewed 6 Sept 2026Sources in this record (4)
- Plaquette ↗
- Yaqumo and QC Design Announce Collaboration to Accelerate Fault-Tolerant Neutral-Atom Quantum Computing ↗
- Plaquette: A hardware-aware design platform for fault-tolerant quantum computers ↗
- C12 Partners with QC Design and Adopts Plaquette to accelerate towards Fault-Tolerant Quantum Computing with Carbon Nanotubes ↗
What it does. Where it fits.
Fault-tolerance design software: hardware noise modeling and QEC simulation
Who should look closer
Quantum hardware and QEC researchers deciding which imperfections or architectural choices matter most.
QubitWire’s editorial assessment of practical fit.Explore Plaquette licensing
Plaquette is a Python software suite. Product documentation directs users to discuss licensing or book a demo; its public technical paper can be read without a software license.
Check the current access route ↗What has been demonstrated
A July 2026 preprint validates simulation methods against full-state reference calculations for selected noise models. Yaqumo separately confirms adopting Plaquette to evaluate its neutral-atom architecture.
What remains unresolved
Predicted logical error rates depend on the hardware model and simulation assumptions. Software adoption and simulated fault tolerance do not establish a working fault-tolerant quantum computer.
The next question to watch
How closely will the model's predicted logical error rates and resource requirements match measured hardware as systems scale?
A research question, not a promised milestone.QubitWire coverage
No published QubitWire stories currently match this organization. The evidence sources below provide the starting point.
Sources & evidence
- Plaquette ↗Organization-originated source · Publication date not stated
Documents a licensed Python simulation suite covering code definition, noise modeling, circuit generation, simulation, decoding and analysis, with multiple samplers and quantum-error-correcting code families.
- Yaqumo and QC Design Announce Collaboration to Accelerate Fault-Tolerant Neutral-Atom Quantum Computing ↗External source (may be a collaborator) · 6 Feb 2026
Yaqumo confirms adopting Plaquette in its R&D workflow for evaluating neutral-atom architectures under realistic noise; future hardware scale is a goal.
- Plaquette: A hardware-aware design platform for fault-tolerant quantum computers ↗Organization-originated source · 9 Jul 2026
Preprint presents the simulation framework, validates XPauli and near-Clifford samplers against full-state simulation, and demonstrates superconducting leakage, neutral-atom scattering and trapped-ion heating models.
- C12 Partners with QC Design and Adopts Plaquette to accelerate towards Fault-Tolerant Quantum Computing with Carbon Nanotubes ↗External source (may be a collaborator) · 16 Mar 2026
C12 confirms adopting Plaquette to benchmark error-correcting codes and refine its carbon-nanotube spin-qubit architecture.
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