Google’s Modular QEC Design Trades a Few Long Links for Far Fewer Qubits

Surface codes fit flat quantum chips, but their protection can consume a huge number of physical qubits. A Google Quantum AI and DeepMind team proposes a middle ground: keep most operations local inside manageable planar modules, then add a sparse set of fixed connections between module boundaries.^[1][2]

Planar islands, hyperbolic code

The construction turns those modules into semi-hyperbolic surface and color codes, aiming to capture the high encoding rate of quantum LDPC codes without demanding a dense web of crossing couplers. The paper centers modules of roughly 100 qubits and supplies syndrome-extraction circuits plus matching and neural-network decoders.^[1][2]

In circuit-level simulations, the design uses ten times fewer physical qubits or better than surface-code memories at the same target logical error rate, even when the inter-module seams are noisier.^[1][2]

The large-system projection is bigger

For larger projected systems, the authors report examples with encoding rate 1/16 and distance at least 22, exceeding the rate and distance of the 288-qubit, 12-logical-qubit, distance-18 two-gross bivariate-bicycle code while preserving mostly nearest-neighbor gates within modules.^[1][2]

Their scaling comparison implies more than a 30-fold overhead reduction relative to surface codes. They also design fault-tolerant walking circuits for logic and an extractor system about 4.5 times smaller than the code block.^[1][2]

None of it has run on hardware

Every headline number comes from simulation or projection. No processor was partitioned into these modules, no seam coupler executed the syndrome circuit and no decoder closed a real-time loop. The comparison depends on assumed physical and seam error rates. Manufacturing, calibration, leakage, crosstalk and control latency could erase some of the modeled advantage.^[1][2]

The decisive experiment is a small pair of planar modules joined by the proposed boundary links, repeatedly running syndrome extraction under measured seam noise. That would test whether the connectivity benefit survives real interconnect errors before extrapolating to dense fault-tolerant storage.^[1][2]