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Welinq speeds up one step in testing modular quantum computers

A reported tenfold GPU gain applies to sampling simulated errors. Decoding and the rest of the workflow still determine the total runtime.

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Equipment cabinets of the Frontier supercomputer at Oak Ridge National Laboratory.
Frontier at Oak Ridge National Laboratory. General high-performance-computing context; this is not the hardware used for Welinq’s reported sampling benchmark.Photo: Frontier supercomputer · OLCF at ORNL · CC BY 2.0Full image credit

Welinq reports an approximately tenfold reduction in the time needed to sample simulated error patterns for selected modular quantum-computing circuits. Its October 20 post compares Stim running on a CPU with NVIDIA CUDA-Q sampling on an NVIDIA L4 GPU. The comparison concerns one computational stage, not a tenfold faster quantum computer.[1]

The reported tests use the same circuit-derived detector error models and sample counts: 50,000 shots, with a maximum code distance of 21. A detector error model describes how faults change the measurement signals used to identify errors and the logical information being tracked. Sampling it generates the many possible outcomes needed for a statistical evaluation.[1]

The associated research studies logical CNOT operations between surface-code patches assigned to different processors. Its simulations model extra noise at interfaces implemented using shared . The version revised October 22 assumes equivalent and specified depolarizing noise channels. Those choices define the modeled system; the work does not report a deployed network passing the same tests.[2]

After sampling comes decoding: a method uses the simulated signals to predict the correction. Researchers compare those predictions with the known simulated outcome to estimate logical failures. The companion paper uses PyMatching for this stage. Faster sampling does not automatically accelerate decoding, model preparation or every other task in the experiment.[1][2]

The distinction can be understood without extrapolating the benchmark. If a hypothetical workflow spent most of its time elsewhere, reducing its sampling time would leave that other work intact. A complete comparison therefore needs the fraction of runtime spent in each stage, alongside matched model inputs, sample counts and statistical uncertainty.

The useful opportunity is to test more architectural choices within a fixed research budget. Welinq acknowledges that total runtime improvement depends on the remaining stages. The next persuasive result would publish a reproducible complete-workflow comparison and show whether faster sampling changes the confidence of an architectural decision. The accompanying preprint first appeared in July; October brought an update and the separate sampling report.[1][2]

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Evidence & context

2 linked sources

Company benchmark and research preprint

How to read the evidence and dates

An announcement records what an organization stated. An experiment reports an observation. A simulation or resource estimate depends on its assumptions. QubitWire’s analysis connects these sources; the labels are not quality scores.

Published is the article’s first QubitWire publication. Updated marks a substantive content change. Sources checked records a review of the underlying evidence. An older paper can support a new explanation, and another press release about the same work is not independent replication.

QubitWire take

Speeding up simulated-error sampling can expand a study, but the complete runtime and the noise model still govern the conclusion.

Sources

  1. Welinq: GPU-accelerated detector-error-model sampling

    October 20, 2026 company benchmark: identical circuit-derived models, 50,000 shots, maximum code distance 21, Stim CPU sampling versus CUDA-Q on an NVIDIA L4 GPU.

  2. Chelluri and colleagues: modular architectures with noisy interfaces, version 2

    Research preprint revised October 22, 2026; first submitted July 29. Circuit-level simulations with stated noise assumptions, not a hardware demonstration.

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