Perfect state transfer names an ideal graph property, not a hardware score
A hardware preprint tests ideal graph-transfer constructions while keeping encoding, phase and noisy performance distinct.
An October 14 preprint implements quantum-walk transfer circuits on IBM's ibm_kingston processor and compares encodings and gate constructions without or mitigation. Some comparison runs are dated May 20–22, so October is the disclosure date, not the date of every experiment. The graphs have ideal perfect or peak transfer properties; measured target probabilities remain a separate result. The processor's total qubit count is not the number transferred. This is a hardware demonstration of mathematical transfer constructions under noise, rather than a claim of experimentally perfect delivery of arbitrary quantum states.[1]
The authors test graph-derived circuits on IBM Heron hardware without error correction or mitigation. The processor has 156 qubits; that is not the number of qubits in the transferred state. Some encoding comparisons were performed on different days, so calibration changes may also affect the observed probabilities. An ideal graph result and a hardware transfer probability need separate labels.[1]
An original two-vertex example is especially transparent. Let the Hamiltonian in the single-excitation basis be J times the Pauli X matrix. Starting at the first vertex, the target probability is sin squared of Jt. At time pi divided by two J, that probability is one in the ideal model, while the target amplitude carries a factor of minus i. This calculation uses an ideal Hamiltonian and exact timing. It supplies a mathematical reference, not a measured transfer probability or a claim about the paper's larger graph circuits.
The phase matters when transferring an arbitrary qubit rather than merely detecting one excitation. A superposition of vacuum and excitation can acquire a relative phase between those components. A known phase can be corrected, but verifying the complete transfer requires checking coherence as well as arrival probability. A high probability of finding an excitation at the target is therefore informative without being a complete quantum-channel characterization. The measurement task should state whether it tests basis-state transport, phase-preserving transfer or a broader family of input states.
Encoding can radically change the implementation cost. A graph's vertices can be represented directly by physical sites or compressed using symmetry into a smaller effective description for a particular task. Such a reduction can preserve selected transfer behavior without reproducing every possible graph state or observable. The hardware saving belongs to that restricted equivalence. A comparison should say which initial states and outputs the encoding preserves and how the required couplings are synthesized, rather than treating the reduced circuit as a full physical realization of every vertex in the original graph.
Digital simulation adds an approximation choice. Splitting an evolution into elementary gate steps can reduce mathematical discretization error as more steps are used. Additional steps also expose the circuit to more physical gate errors. The best hardware setting can therefore use fewer steps than an ideal noiseless accuracy calculation would favor. A useful analysis shows both contributions and checks the simplified error model against measurements. It should not assume that reducing Trotter error necessarily increases the observed target probability on a noisy processor.
Device scale needs equally careful labeling. Running a circuit on a processor with many available qubits does not mean that the circuit occupied them all or transferred that many independent states. Logical graph size, encoded register size, active and total device capacity are different quantities. Each answers a legitimate resource question. Keeping them separate allows readers to compare a symmetry-compressed walk with direct routing or SWAP-based movement without accidentally crediting either method with an unreported network scale.
The study makes an abstract graph property experimentally inspectable. The next useful comparison would include phase-sensitive inputs, matched active resources and a complete account of encoding and gate approximation. Readers could then judge which construction provides the best transfer for the intended task under actual device noise. The term perfect can remain where it belongs in the mathematics, while measured probabilities, coherence and uncertainty describe what the hardware achieved. That distinction preserves both the elegance of the ideal construction and the engineering information in its imperfect realization.