Spin Locking Extends Silicon Spin-Cat Coherence

A silicon antimony-spin preprint reports 225-millisecond coherence for logical |+〉L under spin locking: approximately 19 without protection and 85 with Hahn echo. No active error correction was performed.^[1]

How protection works

Continuous driving shifts sensitivity toward frequencies with weaker noise. A separate pulsed technique cycles spin levels to average dephasing, the scrambling of relative quantum phases.^[1]

Decay of the logical ±i states was not measured, leaving arbitrary logical storage incompletely characterized. The experiment cancels drive-induced phase rotations; future integrations must cancel or track them. Drive errors may weaken the protective noise bias.^[1]

Beyond storage

QubitWire analysis: the useful unit of comparison for an eventual processor is a complete storage-and-use cycle. Extra idle time helps only if entering and leaving the protected regime preserve the information needed later. A design team should therefore budget the protection as a control operation, with its own calibration burden. Longer coherence alone does not establish a computational speedup.^[1]

For example, a longer protected wait could be valuable between operations, but its usefulness should be judged at readout, after all transitions into and out of the protected state have finished.^[1]

The next test

Our proposed next test would prepare six logical input states, alternate protected storage with gates and repeated correction, and compare final logical error rates against matched unprotected sequences. Equal elapsed time and a separate accounting of control overhead would help distinguish reduced idle noise from changes elsewhere in the sequence.^[1]

Reporting the worst-performing input alongside the average would prevent a favorable state from hiding a weak direction. Repeating the comparison across calibration intervals would probe whether the benefit survives routine drift. This proposed benchmark remains to be demonstrated. The reader question is how much of the storage improvement survives a complete logical operation cycle.^[1]