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Stitched surface codes give a quantum memory another layer of checks

A distinct Willow memory experiment connects layered checks, corridor geometry and classical decoding.

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An exposed gold-colored dilution refrigerator hangs in a blue-lit frame with many wires descending through its stages.
Cryogenic equipment at Fermilab’s SQMS Quantum Garage. Superconducting-hardware context; this is not Google’s Willow processor or the stitched-code experiment.Ryan Postel / Fermilab · NQI gallery reuse permissionFull image credit

A preprint submitted on October 15 combines four surface-code patches with an outer code that stores two . Narrow corridors carry verified GHZ ancillas used to measure the outer checks. The authors report simulations and an implementation on a 105-qubit Willow processor; their correlated decoder gives a 1.52-fold reduction in block logical error when the tested distance increases from four to six. This is a specific quantum-memory experiment, separate from Google's magic-state work and from a demonstration of a complete fault-tolerant application.[1]

The hardware test runs the stitched construction in both ZZ and XX memory bases. Its four patches contain 16 data qubits at distance four and 36 at distance six; corridor and measurement qubits add to those counts. The experiment also repeatedly measures and resets some that normally serve as data qubits. That makes the layout a demanding test of the full operating sequence, not just a comparison of two code diagrams.[1]

Adding checks creates work as well as protection. The apparatus has to prepare supporting states, couple them to the data in the right sequence and interpret the resulting records. Errors in those supporting steps can propagate. A useful outer check is consequently more than a line of algebra: it needs an implementation whose own faults are understood. That is why the route used to distribute an ancilla and the schedule for measuring it belong in the engineering description of a memory code.

Geometry enters because information cannot be gathered instantaneously from arbitrary places on a local device. A layout needs space for data and for the operations that connect their checks. Corridors can be thought of as working areas in the layout: they occupy physical sites and have a schedule. A comparison that counts only the stored logical qubits would miss their cost. The useful resource account includes the footprint, supporting preparation, repeated measurement and the time during which different parts of the design are occupied.

An illustrative comparison shows why the unit of failure matters. Suppose a two-qubit memory block fails in 6 out of 1,000 trials under one setting and 4 out of 1,000 under another. The block failure rate has improved by a factor of 1.5. That does not automatically give the failure probability of each logical qubit or of a gate using them. The errors could be unevenly distributed or correlated. These invented counts explain the denominator; they are not the experiment's measured counts or confidence interval.

Distance provides another structural description, but it has to be connected to an operating circuit. A code may require more physical faults to create an undetectable logical error under a specified model. The complete measurement sequence can introduce additional routes through which faults combine. An experimental distance comparison therefore asks whether increasing the structure actually improves the observed logical behaviour under the conditions tested. It is evidence about the implemented memory, while extrapolation to much larger devices remains a further argument with its own assumptions.

The classical decoder is part of that implementation. A syndrome is a record of check outcomes, not a uniquely labelled list of physical mistakes. Decoding chooses an interpretation consistent with the record and a noise model. If two candidate mistakes are correlated, treating them as independent may discard useful information. Conversely, an elaborate decoder can require more computation. Comparing codes should therefore retain the decoding method and its operating cost, instead of presenting the quantum layout as if it were the entire memory system.

The constructive next question is what happens when the stored information is used. A memory must eventually be connected to preparation, logical operations and readout. The interfaces can alter the resource advantage of a promising storage design. Following those interfaces would make a substantive continuation of this work, while simply repeating the distance result would add little. For now, the paper offers a concrete example of how geometry, layered checks and classical inference can be designed together around the same protected information.

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Evidence & context

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Experiment and simulation preprint

How to read the evidence and dates

An announcement records what an organization stated. An experiment reports an observation. A simulation or resource estimate depends on its assumptions. QubitWire’s analysis connects these sources; the labels are not quality scores.

Published is the article’s first QubitWire publication. Updated marks a substantive content change. Sources checked records a review of the underlying evidence. An older paper can support a new explanation, and another press release about the same work is not independent replication.

QubitWire take

The paper makes concatenation tangible: protection is built through a physical schedule, not supplied by a code name alone. The manuscript connects a current experimental result with the practical cost of supporting checks and clarifies why block-level memory performance must remain distinct from application-level reliability.

Sources

  1. Stitched surface codes: planar concatenation through GHZ corridors

    Source dated 2026-10-15; checked October 17, 2026. Bibliographic record, abstract and selected primary main-text passages reviewed. Complete supplements, proof correctness and reproducibility were not independently verified.

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