TETRIS-Q Tries to Box In a Quantum Chip's Radiation Errors
A simulated chip layout uses barriers and shuffled error-correction codes to keep one radiation hit from becoming a whole-chip problem.
A cosmic ray or stray photon can disturb many at once—the kind of correlated burst ordinary struggles to untangle. TETRIS-Q proposes dividing a chip into small zones, then spreading each logical code across those zones so one hit reaches fewer related qubits.
The idea links chip layout and software mapping. Physical phonon barriers are modeled around groups of neighboring qubits, while independent rotated surface codes are interleaved instead of sitting in compact blocks. Designers could trade more barrier material for stronger isolation—or use fewer barriers and smarter placement.
Across more than 51 million STIM simulations, the authors report peak logical-error reductions above 99.8% and an 80% shorter observable transient in selected barrier configurations. A 15-qubit tile with four interleaved codes reached a modeled average logical error rate of 9.3e-4 while cutting barrier-tracing cost by more than 70% versus single-qubit tiles.
This is a design study, not a protected processor. It models a generalized 1,741-qubit square lattice, SI1000-style noise and a severe 100-millisecond radiation event injected at the chip center. The team did not fabricate barriers, run the scheme on hardware or analyze the three-dimensional couplers that interleaving may require. The headline percentages are best-case simulated points, not universal performance claims.
A convincing follow-up would fabricate several tile patterns, expose devices to controlled radiation and compare measured correlated-error bursts with the model. Researchers also need to price the couplers, yield and layout complexity that the simulation leaves outside its cost calculation.