A fast dual-rail gate retains detectable errors
A dated, source-bounded reading of the original report.
A fast dual-rail gate retains detectable errors
- Reported
- D-Wave’s research team reports an approximately 500-nanosecond controlled-Z gate between two dual-rail cavity qubits.
- Supported observation
- The Nature paper reports about 0.5% erasures per gate and residual Pauli errors below 0.1% in its characterization.
- Conditions
- Two encoded qubits use superconducting microwave cavities and a transmon coupler. Residual errors are evaluated after detected erasures are removed; they must be read alongside the erasure rate. Characterization uses state tomography and interleaved randomized benchmarking. Larger-code comparisons are simulated.
Not established
This is not a demonstrated large error-corrected processor. Error behavior worsens at greater repeated-gate depth; the surface-code simulation assumes perfect erasure checks and restricted noise models.
- An entangling gate for dual-rail erasure qubitsNature · Peer-reviewed primary research paper · Source published Source checked
What would change this record?
Repeated logical error-correction cycles on larger hardware with imperfect checks and all operational errors included.
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